We use 3 pieces of AD7172-2.
Because 3 ADCs would like to be sampled simultaneously, we use SYNC pin of AD7172-2.
Plesae let me know your advice how to use SYNC .
I thought that the timing which sets SYNC input low to high transition is before first falling edge of SCLK.
(I thought that SYNC input should be set low to high at red circle in attached timing chart of AD7172-2 datasheet )
But, datasheet P.44 says below
"When multiple devices are being synchronized, take the SYNC input high on the master clock rising edge."
Which edge does master clock rising edge of above description mean in attached timing chart ?
Could you give me your advice about the timing which sets SYNC input low to high ?