I have looked through the many threads pertaining to the DAC sampling on the FMCOMMS1 and I have to admit, I am a little bit confused and I am hoping somebody will help me understand it. I am using FMCOMMS1 running Linux on the ZYNQ with IIO scope running.
1- Can somebody please explain to me how the clocking to the DAC_RFCLK, DAC_CLK, DAC_OUT, and DAC_IN to/from the ZYNQ are generated and related? What does the entry on the IIO Scope Frequency setting really control?
2- Given, the FCOMMS1 design, what is the highest DAC sampling frequency I can use? Anything between 1000 MHz and 1230MHz will be good and how do I go about doing it? Is there an easier way of doing it other than changing the internal registers of the clock distribution.