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FMCOMMS2 HDL RX-ADC PACK dvalid and dsync signals

Question asked by berker on Sep 17, 2015
Latest reply on Sep 18, 2015 by AdrianC

Hi everyone; my question is about timing dvalid abd dsync signals.

dvalid -> fifo_wr_en

dsync -> fifo_wr_sync

How are these 2 signals works?

Is frequency of dvalid related Sample rate of ADC inside 9361 core? or fixed rate?

What is the function of dsync signal?

 

adc_pack.jpg

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