Hi,

I know this is a beginner question, so please don't feel insulted by my state of knowlege. In the FIR chapter in the hardware reference of the 214xx processors I don't quite understand what is meant by hard and soft filter length.

Can someone enlighten me?

Regards,

Peter

Hi Peter,

ADSP-214xx has 1024-TAP length FIR hardware accelerator. The accelerator consists of a 1024 word coefficient memory, a 1024 deep delay line for data, and four MAC units. If you want to implement a 4096 tap length filter, the FIR controller implements 4 iterations of 1024 taps. Here the 1024 taps becomes the hard length and the 4096 is the soft length. Results are computed in multiple iterations when the soft filter length is greater than 1024 (for example, 2048 TAPs on a 1024 hard filter length).

Another example : Say, you have implemented a FIR filter of length of 256 taps and trying to run a 550 tap FIR filter on it. Here the 256 tap is the hard length and the 550 tap is the soft length. FIR controller implements two iterations of 256 taps and one iteration of 38 taps. (If the soft filter length is not a multiple of the hard filter length the controller iterates until the soft filter length is satisfied.)

Regards,

Mahesh