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AD9361 data port (P0/P1) 'default' state queries

Question asked by Cman Employee on Sep 16, 2015
Latest reply on Oct 15, 2015 by tlili

Hello Experts


From data sheet, user manuals etc. e.g. see pictured below). it is not clear what default states these port are in. Please can you advise as they are crucial for interface e.g. to a host processor, else reliability or functional operation may not be guaranteed;


Please can you advise what are the state these (P0/P1) outputs;

(a) When these port are disabled, what (default) state are these port in (i.e. default low, default high, or high impedance (Z) )

(b) when in single port mode Rx mode are they high impedance (open-collector), or  i.e. is there a weak internal pull-up inside the IC or not ?.

(c) when in single port mode Tx mode, when not Transmitting are they default, low ? or high impedance ?.

(d) when in duplex port mode are they high impedance ? e.g. open-collector? if so then external pull-up is required.


As you can see, pending on the configuration options as defined in the documents, user can take precautionary measure and design the interface accordingly.


Thanks and Regards,