AnsweredAssumed Answered

Adding another ip block within FMComms2 HDL RX Line

Question asked by berker on Sep 16, 2015
Latest reply on Sep 16, 2015 by rejeesh

Hi everyone,


There is 12 bits LVDS  for RX line. These signals goes to AXI_AD9361 core. This core outputs 4 different 16 bits IQ data.

For RX1: I0,Q0 and for RX2:I1,Q1. Then these datas packed 64 bits data in the util_adc_pack core. This bus connect to ADC_DMA core.With Master-slave interconnect 64 bits data are write to DDR. OK!!!




But i have some questions?


1) What is the order format of 64 bits data? Like [I0 I1 Q0 Q1] or [I0 Q0 I1 Q1] ..

    16 bits I or Q data's 4 LSB bits is zero,is it true?

2) I want to add a new core between the adc_pack and adc_dma cores.

   This extra core,can be, multiply with 2, a digital filter or fft. Meaningfull or not. I just add a new core loyal to design.

  Here say that:"An optional off-line FFT core may be used to generate a spectrum plot"

How can i do?