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How to set SPORT data as right-justified and sign-extended

Question asked by punkah-wallah on Sep 15, 2015
Latest reply on Oct 14, 2015 by MaheshN

I have an ADSP-21469 EZ-Board and an Audio Extender Board.  I am playing with the "Sharc EZ-Extender_21469 AD1939 C Sampled-Based Talkthru 192 kHz_6serialports" example.  I have made the modifications to the EZ Board switch settings as shown in the readme file and the example works fine.  For each codec, data comes out on the 1st and 3rd RCA jack derived from the first input, on the 2nd and 4th RCA jack derived from the 2nd input, on the 5th and 7th jack from the 3rd input, and the 6th and 8th jack from the 4th input.

(Note: I numbered the output channels from left to right with the middle row being first and the top row second.)

 

However, in my real application, I will need the 24-bit input data to be right-justified and sign-extended.  And unfortunately, I will have no CPU resources available to shift the input data right by 8 bits or to later shift the output data left by 8 bits.  So the shifting and sign-extension must be done by the codec or the SPORT.

 

I have made a tiny change to the example that comes with VisualDSP to have the SPORT attempt to right-justify and sign-extend the input data from the 12 audio jacks on the Audio Extender board.  Changes are as follows:

 

   ADDS_21469_EzKit.h has the following line added:

 

#define RIGHT_JUSTIFY 1  // when 1, right-justify and sign-extend the 24-bit codec data

 

   SPORT01_TDM_init.c, SPORT23_TDM_init.c, and SPORT45_TDM_init.c all have the same change (though the pSPCTLx register numbers change based on which file is being edited):

 

#if RIGHT_JUSTIFY

    *pSPCTL1 =     SCHEN_A | SDEN_A | SLEN24 | DTYPE1;

#else   

    *pSPCTL1 =     SCHEN_A | SDEN_A | SLEN32;

#endif   

 

#if RIGHT_JUSTIFY

    *pSPCTL0 =     SCHEN_B | SDEN_B | SCHEN_A | SDEN_A | SPTRAN | SLEN24 | DTYPE1;

#else   

    *pSPCTL0 =     SCHEN_B | SDEN_B | SCHEN_A | SDEN_A | SPTRAN | SLEN32;

#endif   

 

So when RIGHT_JUSTIFY is set to 1, the 6 SPORTs are set to use SLEN24 and DTYPE_1 instead of SLEN32.  There are no other changes.  My impression is that this should cause the input data to be right-adjusted and the top 8 bits should be sign bits to match bit 23. On output, I'm not exactly sure what it really means, but what I want is for the volume not to change due to the input data being right-justified.

 

The results that I get are quite unexpected and I don't understand why.  Rather than getting 8 channels of output on each of the 3 codecs, I only get 3 channels of output.  The first output channel is derived from the first input channel.  The 2nd output channel is derived from the second input channel.  The 7th output channel is derived from the 3rd input channel.  Any other output channels are quiet or static.

 

If I only set the input SPORTs (i.e. SPCTL1, SPCTL3, and SPCTL5) to "SLEN24 | DTYPE1" and leave the 3 output SPORTs as "SLEN32", then I get the behavior that I would have expected on output channels 1 and 3 only.  They both come from input channel 1, but they both have extremely low volume.  None of the other output channels work at all.

 

So how do I configure the AD1939 or SPORTs so that the input can be 24-bit right-justified and the output will have the same volume as the input?

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