I have a design which includes an IP block obtained from system generator. The inputs to the design are given from the processor using the AXI interface. Now, I would like to transfer the output to the FMCOMMS-3 board.
This is how I want the data to travel:
processor (inputs) - > Programmable Logic (output) - > FMCOMMS-3
To facilitate this, do I need to send the output data of the PL to the FIFO defined in FMCOMMS-3?
Or is there an efficient way to do this?
Also, It would be really great if there is a reference design which does the same thing described above.
Any help is appreciated.