I would like to check if using AD9250 requires end user certificate?
Also if I were to use multiple chip, any advise on the synchronization?
As for JESD204B, does it require the user to purchase a separate IP core?
The JESD204B subclass 1 allows for deterministic latency which is used to synchronize multiple AD9250’s using SYSREF. You will need to keep clock and SYSREF inputs aligned to all AD9250’s.
Regarding the IP core for the JESD204B, the AD9250 includes the transmit portion of the link, if you use an FPGA for the receiver portion of the link you should consult the FPGA manufacturer on costs for their IP. Both Xilinx and Altera have a JESD204B IP core and both do charge for it I believe, but it is best to check with them.
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