I am using a BF547 DSP with 13MHz clock input. I have yet to find a PLL/Divider setting that gives exactly 8000Hz for the CODEC interface. Is there such setting to get me exactly 8 kHz?
Thank you and best regards,
It means you want TSCLK to be 512 KHz. You just have to change TLKDIV acoordingly to a lower value.
I don't know what are you exact SCLK and CCLK requirements but you can give a try with the settings given below (for 533 MHz part).
giving core CLK= 416MHz, SCLK= 32 MHz and Sport clk=8 KHz.
The SCLK needs to be from 120MHz to 130MHz according to the BF547 specification (we are using mobile DDR). So this solution won't work. Thank you for your reply.
For the given SCLK requirement may be following settings will work:
SCLK= 125.6 MHz and
Sport clk =8.004KHz.
Thank you for helping me out. I am sorry I wasn't very specific about the SPORT clock. The clock I am after is the TFS clock (frame sync). The TSCLK will be 64xTFS or 512 kHz.
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