I'm using a fpga stratix iii to control ad9914 and now i wand to use the sync_clk signal to clock a vhdl block and synchronize it with the DDS.
So i have a problem because the FPGA accept signal with symetical amplitude (Vpp/eg:-1.3V/1.3V) and i think the DDS generate a sync_clk with no symetrical amplitude (Vrms = 962mv = (0V/2.72Vpp)).
When i send that signal at input data clock on the fpga; it is not recognize.
Is there anyone who can help me??