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AD7961 Reference Design Gated Clock

Question asked by stenoaux on Sep 14, 2015
Latest reply on Sep 15, 2015 by rejeesh

I recently downloaded the AD7961 reference design from the Analog WIKI (AD7961 Native FMC Card & Xilinx Reference Design [Analog Devices Wiki]) using the Echoed Clock variant.

 

Diving into the Verilog code provided for the AD7961, I see the design is using an AND-gated clock to output the CLK+/- signal from the FPGA to the ADC.  This has caused ISE 14.7 to issue an error saying:

 

Place:1136 - This design contains a global buffer instance, <clk_gen/clkout2_buf>, driving the net, <clk_200_0000MHz>, that is driving the following (first 30) non-clock load pins.

< PIN: vid1_AD7961/fast_clk_i_clk_s_AND_20_o1.A4; >

< PIN: vid2_AD7961/fast_clk_i_clk_s_AND_20_o1.A4; >

This is not a recommended design practice in Spartan-6 due to limitations in the global routing that may cause excessive delay, skew or unroutable situations.  It is recommended to only use a BUFG resource to drive clock loads. If you wish to override this recommendation, you may use the CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote this message to a WARNING and allow your design to continue.

< PIN "clk_gen/clkout2_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >

 

I have attached the code in question, and copied the relevant sections here:

 

assign clk_s            = ((serial_present_state == SERIAL_READ_STATE)&&(sclk_cnt > 5'd0)&&(buffer_reset_s != 1'b1)) ? 1'b1 : 1'b0; 

...

// Clock Out Single -> LVDS   

OBUFDS

    #(

        .IOSTANDARD("LVDS_25"),     // Specify the output I/O standard

        .SLEW("FAST")               // Specify the output slew rate

    )

    Clock_Out_OBUFDS

    (

        .O(clk_pos_o),              // Diff_p output (connect directly to top-level port)

        .OB(clk_neg_o),             // Diff_n output (connect directly to top-level port)

        .I(fast_clk_i & clk_s)      // Buffer input

    );

 

Does anyone know if there is something inherently different about the Spartan-6 and Kintex-7 that would make this clock gating method toss an error for Spartan-6, but be acceptable for Kintex-7?  I could not find any constraint in the reference design project that was overriding the CLOCK_DEDICATED_ROUTE error.  Which makes be believe the reference design project has no issues with this implementation.

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