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AD9739 glitches

Question asked by Davidh1901 on Sep 14, 2015
Latest reply on Nov 12, 2015 by danf

We have problem with the AD9739 DACs. We are operating them at 2.5 GSps. The DAC is being driven by a Virtex 7 FPGA. To ensure signal integrity between the FPGA and DACs, we tune the odelay in the FPGA to the center of the eye for each LVDS bit.

We measure the location of the center of the eye by looping the output of the DAC back via an ADC and looking for errors in a test waveform.

Most of the time everything works.

However, on some devices – in particular, a device that has been deployed in a commercial system – the DAC regularly comes up in a bad state. There are several distinct bad states that the device displays :

  • - Sometimes the eye is narrow, only about 200ps.
  • - Sometimes the eye is bad everywhere, with the errors at a rate of about 10 per second even when the FPGA odelays are optimum
  • - Sometimes it dribbles errors at a rate of 1 or 2 per second.


When it comes up well, the eye is about 500ps wide.


Re-initializing the mu controller setup kicks the DAC into a new state. On the worst device, it comes up in a good state about 1 in 4 times.

Re-initializing the data receiver controller does not change the state of the DAC. If the eye is narrow, it remains narrow no matter how many times we re-initialize the data receiver controller.


In the bad state, the errors may only occur at a few per second, so scanning the eye across many bits takes minutes.


The bad state is dependent on the delay of the DCI clock pin on the FPGA. If I set different values for the FPGA odelay for the DCI pin, then I see the behaviour below :

Note that :

  • The DAC has not been reset or reprogrammed for the different lines of the table below
  • When I change the FPGA odelay for the DCI pin to the DAC, I also change the odelays for the corresponding data pins going to the DACs
  • Each tap of the FPGA odelay corresponds to a delay of about 70 ps
  • The values in the table below are repeatable (for a given DAC setup). i.e. every time I set the DCI odelay to 10, the data eye width is zero.
  • The eye width has been determined from about 1 seconds worth of data. Where the eye is narrow (say at DCI odelay setting of 10), there is still a region of where the error rate is quite low – where only about 1 in 10,000,000 bits are wrong.


FPGA DCI odelay    data bit eye width       DCI setting

(FPGA odelay taps) (FPGA odelay taps)  (as read back from DAC registers 0x1B and 0x1C)

2                            3                               158

3                            6                               164

4                            7                               169

5                            3                               175

6                            6                               181

7                            6                               190

8                            6                               195

9                            6                               201

10                          0                               206

11                          6                               211

12                          7                               216



If I set the FPGA DCI odelays to one of the settings where the eye is wide, then it seems that rerunning the DAC setup (i.e. the mu setup procedure) always results in the DAC coming up with a wide eye.

But if I set the FPGA DCI odelay to one of the settings where the eye is narrow, then rerun the DAC setup, then sometimes it comes up with a wide eye and sometimes it comes up with a narrow eye.