I'm performing a timing analysis the JDATA interface between an ADV212 and a Xilnx FPGA - the ADV212 is in encode mode. MCLK = 27MHz, JCLK = 108MHz. I'm using Figure 19 (page 14), Rev. B datasheet for reference.
I'm used to output data havinga clock-to-output type delay from a clock edge, rather than a setup and hold time either side of a clock edge. The values suggest data will be valid for a minimum of 3ns either side of the rising edge of MCLK. Is this really the case, particulalry when MCLK is 27MHz (~37ns period)? I have a setup time of 1.4ns to achieve at the FPGA input so I only have 1.6ns of play to account for tracking delay and any compensation between the IBIS model test load and the actual circuit loading. Bearing in mind the clock originates from the FPGA, the 1.6ns is shared between the clk propagation delay (FPGA to ADV212) and data propagation delay (ADV212 to FPGA). It's all a bit tight, my analysis suggests that I am going to fail the setup time at the FPGA, and I can't hep thinking the window in which the JDATA is valid is much larger than the datasheet suggests. Any help would be much appreciated.