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Clock Constraints in Xilinx Vivado AD9364

Question asked by thisguy on Sep 11, 2015
Latest reply on Sep 16, 2015 by thisguy

Here is the specifications of our setup. We have the Vivado project and XSDK API for the FMCOMMS4 (AD9364 Chip) on a ZC706 eval board up and running. We have began the process of integrating custom DSP Verilog and this requires using the RX clock from the

FMC card to generate synchronous clocks to run our custom logic via an MMCM. An excerpt from the constraints file for these clocks are as follows:

 

create_clock -name rx_clk              -period  4.00  [get_ports rx_clk_in_p]

create_clock -name ad9361_clk     -period  4.00  [get_pins i_system_wrapper/system_i/axi_ad9361/clk]

create_clock -name fmc_dma_clk  -period  10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]

create_clock -name ps7_clk_2       -period 10.00  [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[2]]

 

According to this post https://ez.analog.com/message/209849#209849 the clock rate for the AD9364 is 122.88MHz. I understand that this constraints file is generic to the 9364 and the 9361. However, because my MMCM is expecting 122.88MHz and the clock rx_clk_in_p has a constraint on it for 250MHz an error is generated during implementation about the input clock rate of rx_clk_in_p which ultimately becomes the input to the MMCM after some buffering. I thought that I could just change the constraints as follows:

 

create_clock -name rx_clk              -period  8.00  [get_ports rx_clk_in_p]

create_clock -name ad9361_clk     -period  8.00  [get_pins i_system_wrapper/system_i/axi_ad9361/clk]

 

This alleviated the MMCM error and the project built just fine, however when running the API software the following error was generated

 

ad9361_auxadc_setup

ad9361_dig_tune: Tuning TX FAILED!

ad9361_bist_loopback: mode 0

ad9361_set_trx_clock_chain

ad9361_clk_factor_set_rate: Rate 245760000 Hz Parent Rate 983040000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 122880000 Hz Parent Rate 122880000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 30720000 Hz Parent Rate 61440000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rssi_setup

 

This causes the output of the RX path to shut down. No output data comes from the ADC in this case until I rebuild the project with the original constraints.

 

I also tried to constrain the input to the MMCM by adding additional constraints like so:

    

create_clock -name rx_clk              -period  4.00  [get_ports rx_clk_in_p]

create_clock -name ad9361_clk     -period  4.00  [get_pins i_system_wrapper/system_i/axi_ad9361/clk]

create_clock -name fmc_dma_clk  -period  10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]

create_clock -name ps7_clk_2       -period 10.00  [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[2]]

 

create_clock -name adi_clk122   -period  8.00  [get_pins adi_clk_gen/clk_in1]                              # MMCM CLK_IN

set_input_jitter                               [get_clocks -of_objects [get_ports adi_clk_gen/clk_in1]] 0.1    # CLK_IN JITTER

 

This built just fine, but now I get an additional RX error in the API output:

 

ad9361_auxadc_setup

ad9361_dig_tune: Tuning RX FAILED!

ad9361_bist_prbs: mode 0

ad9361_bist_loopback: mode 1

ad9361_calculate_rf_clock_chain: requested rate 10000000 TXFIR int 1 RXFIR dec 1 mode Nominal

ad9361_calculate_rf_clock_chain: 1280000000 80000000 40000000 20000000 10000000 10000000

ad9361_calculate_rf_clock_chain: 1280000000 80000000 40000000 20000000 10000000 10000000

ad9361_set_trx_clock_chain

ad9361_bbpll_set_rate: Rate 1280000000 Hz Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 1280000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 80000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 10000000 Hz Parent Rate 20000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rssi_setup

 

 

ad9361_auxadc_setup

ad9361_calculate_rf_clock_chain: requested rate 61440000 TXFIR int 1 RXFIR dec 1 mode Nominal

ad9361_calculate_rf_clock_chain: 983040000 491520000 245760000 122880000 61440000 61440000

ad9361_calculate_rf_clock_chain: 983040000 245760000 122880000 61440000 61440000 61440000

ad9361_set_trx_clock_chain

ad9361_bbpll_set_rate: Rate 983040000 Hz Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 491520000 Hz Parent Rate 983040000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 245760000 Hz Parent Rate 491520000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 61440000 Hz Parent Rate 61440000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rssi_setup

 

 

ad9361_auxadc_setup

ad9361_dig_tune: Tuning TX FAILED!

ad9361_bist_loopback: mode 0

ad9361_set_trx_clock_chain

ad9361_clk_factor_set_rate: Rate 245760000 Hz Parent Rate 983040000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 122880000 Hz Parent Rate 122880000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 30720000 Hz Parent Rate 61440000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rssi_setup

 

Am I correct in assuming the input RX clock from the FMC card is 122.88MHz? If so, what would be causing the "ad9361_dig_tune: Tuning TX FAILED!" error? What else can I try to alleviate this problem?

 

Thanks!

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