We have recently purchased an EVAL-AD7671EDZ which is sampling at 1MSPS. The issue is that the SCLK (synchronization clock) signal does not go low enough in its LOW state to allow unequivocal detection of that state. I have attached a screenshot of the SCLK taken from the buffered output (TP17) It should go down 16 times as the data is packed as a 16 bit word. I was hoping using pull-down resistors will solve the issue but it does not seem to make an appreciable difference.
Can anybody suggest a workaround this please? Without a proper SCLK I am unable to unpack the data correctly from SDOUT.
Thanks a lot,