Hi every body,
I'm using the FPGA Stratix III to control the DDS AD9914, and since some week i have found a problem with the PLL,that is locking on a fixed value. When i look the SYNC_CLK on my scope there is always 110MHZ even when i change the multiplier value from 10 to 255. the SYNC_CLK values does not change.
Another problem that i had before the PLL began to locked on a bad value is that the PLL dislocked after few min when the system running.
When i disable the PLL,all thing work fine
Is there anyone who can help me to solve this problem