I have a question about ADV7390 CLK input.
At this discussion...
I was told that I have to input CLK while the device is RESET.
Is this sure?
If is it sure can you give me an advise why do I have to input the CLK signal while the device is RESET?
Generally I think the digital circuit have a asynchronous reset.
So, I think it doesn't care to input CLK while reset is active.
And I think while reset is active , I don't to have input CLK signal.
Before release the reset , I think I have to input the CLK signal.
Can you give me some advise about this?