How good does my input signal need to be?
[The clock ICs with a PLL on-chip, along with an external VCO/VCXO and loop filter, allow for the cleaning up of a jittery clock reference, which is then divided, delayed and distributed by the distribution section of the IC. Other questions in this FAQ address the clock cleanup process. This question will address the distribution section only.]
The clock distribution channels of the ADI clock ICs have very low additive phase noise or jitter. However, these circuits can only add noise (jitter and phase noise), not subtract it. The output from the distribution section can be nearly as good in jitter as the input. We specify this as "additive jitter" or "additive phase noise". The additive jitter of an LVPECL output is around 215 fs RMS.
Random noise adds to random noise as the root sum of the squares (RSS). So the input jitter must be RSS'd with the additive jitter of the clock channel to get the resulting clock signal jitter at the output.
So, your input clock signal needs to be good enough so that when the additive jitter of the clock channel is RSS'd with it, that the result is within your system tolerance.
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