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fmcomms2/zc706 DAC DMA doesn't meet timing

Question asked by jtrimble on Sep 8, 2015
Latest reply on Sep 9, 2015 by CsomI

Hi all,

 

I'm working on a project using the FMCOMMS3 with the Xilinx zc706 board.

 

We've recently needed to upgrade to Vivado 2015.2 to take advantage of some updates in that revision.  I know that official support for 2015.2 in ADI's hdl "master" stable branch isn't expected until the end of this year, but I've begun using the "dev" (unstable) branch from the hdl repo because it builds cleanly under Vivado 2015.2 (and "master" does not due to Vivado 2015.2 TCL API deprecations).

 

When I built the fmcomms2/zc706 project recently (as of commit f1d416a98b), the design failed to meet timing (some paths involved in DAC were failing between the axi_dmac and the axi_ad9361 cores).  Using a much older version of the "hdl" repo (commit 4a9c4cdf), I've been able to use the axi_dmac cores for DAC/TX under a Vivado 2014.4 design just fine, so perhaps this has something to do with recent changes to axi_dmac?

 

I'm able to get by without DAC DMA support for now (and was able to remove the associated axi_dmac cores and get the design to meet timing), but I was just curious if anyone is looking into this issue and when it might be resolved.

 

Thanks for providing the ADI "hdl" reposiotry on github -- it's been a great resource and saved our company lots of work.

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