How do you determine the bandwidth over which phase noise is integrated to obtain jitter?
It is a little tricky to specify the bandwidth over which phase noise should be integrated in order to calculate the jitter which will actually be observed when that clock signal is used to clock a converter. There are many variables which are seldom known with accuracy – such as the inherent bandwidth of the sample clock circuit on the converter. Also, it is very difficult to actually measure the broadband phase noise of a clock signal beyond an offset of a few MHz. If there is an application spec which defines the bandwidth (as is the case, for example, with the SONET/SDH optical networking specs) then use those limits. However, for a true "broadband" jitter calculation some assumptions and simplifications must be made. One assumption made by ADIsimCLK, for example, is that the upper offset integration limit is one-half the clock frequency. The lower offset integration limit is assumed to be between 100 Hz and 1 kHz.
The match between the ADIsimCLK calculation based on these phase noise offset limits is in good agreement with the jitter measurements made using an entirely different whole-system method based on measuring an actual ADC SNR when driven by a clock signal with a measured phase noise spectrum (insofar as that measurement extends in offset). The match between calculated and measured jitter using ADIsimCLK is less than 2 dB.
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