I'm working on AD9265-ZC706 example design, and made some changes on it: add a ddc module to handle
ADC data then put ddc data to ADI dma.
DDC data is formed to frames, length from 64 to 8192, with extra 6*32bit frame head, including a 32 bit frame counter.
That say the actual frame length is from 70 to 8198 * 32bit .
The dma flow is as follows:
Linux OS : create a libiio buffer, specify the buffer length to actual frame length , eg. 70,
Call libiio function: iio_buffer_refill()
PL DMA has enough data length , begin to upload data to PS
PS iio_buffer_refill() returns and begin to copy buffer to ram, compare frame count in the data stream
Problem occurs! The frame count express that the frame lost, though frame head are always align!
eg. current frame count is 8836, the next should be 8837, but actually I get a 8895-
The PL sends the frame data at a 1ms interval, that's say in a 1024+6 length frame mode, the data rate is
1030 * (32/4) * 1000 , about 4MB/s. This data rate can hardly be too high for DMA transfer.
Actually from anther discussion I see DMA can work to 800MB/s!
If change the interval from 1ms to 3ms, buffer does not lose frames!
Before post this discussion, I googled and read a lot discussions on the EZONE, but sorry I didn't find a solution.
The PL DMA config to has a 512 byte burst length with 4x buffer.
Can some one give me some tips ?