What is system calibration and how is it implemented on the AD779x ?
System calibration allows the converter to compensate for external system gain and offset errors, as well as its own internal errors. Calibration is basically a conversion process on two specific input voltages (zero-scale or offset calibration, and full-scale calibration) from which the offset error coefficient and full-scale error coefficient are determined. With system calibration, the zero-scale voltage and full-scale voltage must be applied to the ADC by the user.
System calibration is a two-step process. The zero-scale point must be presented to the converter first. This voltage is applied to the analog input of the converter before the zero-scale system calibration step is initiated and must remain stable until the step is complete. System calibration is initiated by writing the appropriate values to the MD2, MD1, and MD0 bits of the mode register. The DRDY output from each device indicates when the step is complete by going low, or the mode bits can be monitored via software—these return to idle mode when calibration is complete. After the zero-scale point is calibrated, the full-scale point is applied; and the full-scale system calibration process is initiated by again writing the appropriate code to the MD bits. The full-scale voltage must be set up before the calibration is initiated and it must remain stable throughout the duration of the calibration. DRDY goes low at the end of this second step to indicate that the system calibration is complete.
The calibration procedure is dependent on whether unipolar mode or bipolar mode is used. In the unipolar mode, the system calibration is performed between the two endpoints of the transfer function; while in the bipolar mode, it is performed between midscale and positive full-scale.
When performing a system calibration, the zero-scale voltage and full-scale voltage must be switched into the analog input channel of the ADC. This can be performed by using a low RON SPDT (single-pole double-throw) CMOS switch. One of the switch inputs can be connected to the analog input, which represents the full-scale value, while the other input can be connected to the zero-scale voltage. Using this switch ensures that the signal chains on both analog inputs for the zero-scale calibration and full-scale calibration are identical. By so doing, the system zero-scale calibration will compensate for the insertion loss of the switch. The ADG736 is a dual SPDT switch with a RON < 4 Ω and matching of better than 0.4 Ω.
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