AnsweredAssumed Answered

AD9467 ethernet connection problem

Question asked by -2dbc on Sep 5, 2015
Latest reply on Sep 8, 2015 by -2dbc

Hi all,

 

I have AD9467 and KC705 dev. board. I'm using win7 with cygwin(for linux style make calls.)

I generated bitstream by using reference design hdl codes.(First by using vivado 2014.4.1 and later I upgraded it to vivado 2015.2)

I made required changings on AD9467 for using internal clock.

I programmed FPGA.

I'm also using no-OS software.

I executed your SDK demo and I saw uart results to my console.

I also executed ILA in reference design and I saw signal changings When I changed the signal frequency on signal generator.

 

I have two questions about AD9467 reference design:

1-) ILA ok, uart connection ok but I could not connect via Ethernet. I tried to find correct IP configuration but I could not find it.

Some documents say "Board's IP is 192.168.1.10 and You have to use 192.168.1.100",

xemaclite_ping_reply_example say "The local IP address is set to 172.16.63.121"

I tried both of them; Windows sends packet, but It can not receive any packets.

I read a post in your forum. "If you are in trouble about ethernet connection, You can use DHCP enabled network."

I used my internet modem for this purpose, I disabled all firewalls e.t.c. and tried to connect board but result is same.

I tried IIO Oscilloscope for connecting over ethernet but I didnt worked also.

How can I connect over ethernet, Please help me.

 

2-) I monitored signal changings on vivado's ILA section. Although I feed AD9467 with sinus , I could not monitor pure sinus on ILA.

I know ILA has 32 bits instead of ADC's 16 bit and there are some additional purposes. For example It aims to support high frequecies.

There is a FIFO before it...

My question is simple. Is it possible to monitor pure sinus on this ILA. For example "Yes, You can use  1 to 16 bits for this purpose" or something else...

 

Thanks in advance.

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