I've been going through the data sheet, and I've noticed some discrepancies, wondering if you could clear them up for me. See below:
VREF ISSUES - Seems that there are inconsistancies, could you let me know what is correct for each issue highlighted by different colors.
DAC UPDATE RATE ISSUE - it seems that both of these can't be true. Which one is correct?
ENABLE PINS - In the AFE_CFG register how do BUF_EN, INAMP_EN, TIA_EN control their respective components? Through enable pins not shown in any of the figures?
QUESTIONS ABOUT ADC - I pieced this together base on the figures and descriptions, does this look right? Any idea how the enables play into this?
WAVEFORM GENERATOR AND DAC - Also pieced this together, does everything look OK?
Any commments/questions on this would be much obligied. Maybe there are more block diapgrams that didn't get put in the datasheet/userguide you could send out?