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AD9910 Synchronizing sync_in with ref_clk

Question asked by Kieran.Garrood on Sep 3, 2015
Latest reply on Nov 18, 2015 by Kieran.Garrood

Hi All

I am using the AD9910 in a system that needs to have the DDS synchronized with an ADC so that the waveform time of flight can be measured.

I have a 50 MHz clock signal shared between the ADC and the DDS (ref_clk), the DDS uses the internal PLL to generate a sys_clk of 1 GHz. I also have a trigger signal that is shared and edge aligned with ref_clk. This triggers the DDS to generate the waveform (with profile 0 pin) and ADC to start sampling the waveform. I need the sync_clk of the DDS synchronized with the ref_clk so it will react to the trigger with consistent latency.

Can I use the sync_in pins of the AD9910 to synchronize the sync_clk with the ref_clk?

Will the the synchronization receiver work correctly if sync_in is driven by the same 50 MHz clock as ref_clk, which is 1/20 of the sys_clk?

Are there any other constraints of the synchronization signals that will I need to consider?

This assumes that I will be able to add appropriate LVDS drivers for correct levels, set up times, and hold times etc.

The AD9910 data sheet only describes the use of sync_in when driven by sync_out which is 1/16 of the sys_clk. Is this the only frequency it will work with?

Also what do the values of the "Sync state preset value" of the "Multichip Sync" register represent?

Thank you for your time and help.