A custom board with the AD9361 was created using the FMCOMMS3 as a baseline. The crystal on the board has the same load capacitance and ESR as the one on the FMCOMMS3 board with the updated reference_clk_rate value, but the frequency is 30 MHz not 40 MHz. I try running the code I had working successfully on the FMCOMMS3 board on this custom board and it passes ad9361_setup, but fails tuning. I've output the clk_out and see it's at the correct frequency, but see that it occasionally briefly changes its DC offset before returning to its normal offset. I checked this on an oscilloscope. What could help fix this?

We tried using the crystal that was on the FMCOMMS3 board, but the Xilinx SDK stops running after a few seconds with the custom board with that crystal.

I get the following errors when I run my code. Do you have any recommendations?

ad9361 Setup Complete

AXI_ADC_NOT_PRESENT: axiadc_post_setup called

size: 16

field[0] = 1 cnt = 0 max_cnt = 0 start= -1

field[1] = 1 cnt = 0 max_cnt = 0 start= -1

field[2] = 1 cnt = 0 max_cnt = 0 start= -1

field[3] = 1 cnt = 0 max_cnt = 0 start= -1

field[4] = 1 cnt = 0 max_cnt = 0 start= -1

field[5] = 7 cnt = 0 max_cnt = 0 start= -1

field[6] = 0 cnt = 1 start = 6

field[7] = 0 cnt = 2 start = 6

field[8] = 0 cnt = 3 start = 6

field[9] = 0 cnt = 4 start = 6

field[10] = 0 cnt = 5 start = 6

field[11] = 0 cnt = 6 start = 6

field[12] = 0 cnt = 7 start = 6

field[13] = 0 cnt = 8 start = 6

field[14] = 0 cnt = 9 start = 6

field[15] = 0 cnt = 10 start = 6

size: 16

field[0] = 1 cnt = 0 max_cnt = 0 start= -1

field[1] = 1 cnt = 0 max_cnt = 0 start= -1

field[2] = 1 cnt = 0 max_cnt = 0 start= -1

field[3] = 1 cnt = 0 max_cnt = 0 start= -1

field[4] = 1 cnt = 0 max_cnt = 0 start= -1

field[5] = 1 cnt = 0 max_cnt = 0 start= -1

field[6] = 1 cnt = 0 max_cnt = 0 start= -1

field[7] = 1 cnt = 0 max_cnt = 0 start= -1

field[8] = 1 cnt = 0 max_cnt = 0 start= -1

field[9] = 1 cnt = 0 max_cnt = 0 start= -1

field[10] = 1 cnt = 0 max_cnt = 0 start= -1

field[11] = 1 cnt = 0 max_cnt = 0 start= -1

field[12] = 1 cnt = 0 max_cnt = 0 start= -1

field[13] = 1 cnt = 0 max_cnt = 0 start= -1

field[14] = 3 cnt = 0 max_cnt = 0 start= -1

field[15] = 7 cnt = 0 max_cnt = 0 start= -1

size: 16

field[0] = 2 cnt = 0 max_cnt = 0 start= -1

field[1] = 2 cnt = 0 max_cnt = 0 start= -1

field[2] = 2 cnt = 0 max_cnt = 0 start= -1

field[3] = 2 cnt = 0 max_cnt = 0 start= -1

field[4] = 2 cnt = 0 max_cnt = 0 start= -1

field[5] = 2 cnt = 0 max_cnt = 0 start= -1

field[6] = 2 cnt = 0 max_cnt = 0 start= -1

field[7] = 2 cnt = 0 max_cnt = 0 start= -1

field[8] = 2 cnt = 0 max_cnt = 0 start= -1

field[9] = 2 cnt = 0 max_cnt = 0 start= -1

field[10] = 2 cnt = 0 max_cnt = 0 start= -1

field[11] = 2 cnt = 0 max_cnt = 0 start= -1

field[12] = 2 cnt = 0 max_cnt = 0 start= -1

field[13] = 2 cnt = 0 max_cnt = 0 start= -1

field[14] = 2 cnt = 0 max_cnt = 0 start= -1

field[15] = 2 cnt = 0 max_cnt = 0 start= -1

size: 16

field[0] = 2 cnt = 0 max_cnt = 0 start= -1

field[1] = 2 cnt = 0 max_cnt = 0 start= -1

field[2] = 2 cnt = 0 max_cnt = 0 start= -1

field[3] = 2 cnt = 0 max_cnt = 0 start= -1

field[4] = 2 cnt = 0 max_cnt = 0 start= -1

field[5] = 2 cnt = 0 max_cnt = 0 start= -1

field[6] = 2 cnt = 0 max_cnt = 0 start= -1

field[7] = 2 cnt = 0 max_cnt = 0 start= -1

field[8] = 2 cnt = 0 max_cnt = 0 start= -1

field[9] = 2 cnt = 0 max_cnt = 0 start= -1

field[10] = 2 cnt = 0 max_cnt = 0 start= -1

field[11] = 2 cnt = 0 max_cnt = 0 start= -1

field[12] = 2 cnt = 0 max_cnt = 0 start= -1

field[13] = 2 cnt = 0 max_cnt = 0 start= -1

field[14] = 2 cnt = 0 max_cnt = 0 start= -1

field[15] = 2 cnt = 0 max_cnt = 0 start= -1

SAMPL CLK: 61440000 tuning: TX

0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:

0:# # # # # # # # # # # # # # # #

1:# # # # # # # # # # # # # # # #

ad9361_dig_tune: Tuning TX FAILED!

c0 = 0 c1 = 0

ad9361_init : AD9361 initialization error

Hi, I figured out the issue. One bank on the FPGA wasn't getting power. Thanks for all of the help