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SYNC_CLK Output of AD9914

Question asked by logan on Sep 3, 2015
Latest reply on Sep 3, 2015 by LouijieC

I want to syncronize two AD9914.  But when I look at the SYNC_CLK signal with my scope, this two clock signals look strange.

In the Datasheet it is not clear if sync_clk should be lvcmos33 standard??

The osci measures only 2.16V (Evalboard#1) or 1.58V (Evalboard#2).

The Duty Cycle is also different (30% vs. 36%).



If I enable Impedance 50Ohm in the osci, the signal levels are: 568mV (Evalboard#1) and 616mV (Evalboard#2).

Surprisingly, both duty cycle are now ~25%!!



Is this the expected behavior? In the Datasheet the Value for the Duty Cycle is 45-55%