I have the FMCOMMS2 test design, oscilloscope, and related infrastructure building and working so the build chain is known good. I'm trying to build a transmit (TX) design using the TX1A port of the FMCOMMS2. RX is unused for the moment. In this design there is a Xilinx system generator block generating TX I/Q samples directly into the ADI-provided block axi_ad9361, using the dac_data I/Q 16-bit ports. I've got the full up Linux design running, so driver API commands are all available.
Currently the sysgen block is just a DDS as shown in the Sysgen file, and the complete Vivado design is as shown in the Vivado file. Here are the settings I make to the DAC on the AD9361:
# Configure TX RF bandwidth to 2MHz
echo 2000000 > out_voltage_rf_bandwidth
# Configure TX sample rate to 10MSPS
echo 10000000 > in_voltage_sampling_frequency
# Configure TX RF frequency to 200MHz
echo 200000000 > out_altvoltage1_TX_LO_frequency
What else should I be doing to have the ad9361 directly take I/Q samples as they come in and process them? All the filtering, etc. in the datapath can be configured too, but I was hoping to save that for later. Is there an example of just this being done, without the use of memory buffers storing samples as sent from the CPU?