I just try to interface the AD7960 with Zynq 7z030 from Picozed. I downloaded the reference design which is for a microblaze project in Xilinx Platform Studio. From the pcore directories I used the verilog files to rebuild the axi_ad7960 IP Core within the Vivado IP Generator:
axi_ad7960.v (as top module)
Everything is synthesized and implemented fine. But the PROBLEM is whenever I want to access a register from that IP the Zynq freezes. Under Linux I used devmem and peek/poke to read a register and the board freezes. Even in a baremetal project the board freezes when I access a register. All of my other custom axi IP core work fine.
Does anyone know where the mistake is. Or can anyone provide some information on how to interface the ad converter together with dma transfer under linux?