The data sheet says "A discontinuous SCK is recommended because the part is selected with CNV low, and SCK activity begins tto write new configuration word and clock out data". This sentence by itself is very confusing. What are the implications if the clock runs continuously but with small pauses at precious points - where recommended (see below)?
However, in the same chapter on page 22 it says "... it is recommended to keep the digital pins quiet for approx 20ns before and 10ns after th rising edge of CNV, using a discontinuous SCK..."
I have an application where the SPI bus is shared (timevise and parallel - nor chained) with another device. This means that the SCK would toggle also during inactive periods. The two devices (this AD7949 and another device) share the same DIN, SDO and SCK pins, but the other device is enabled only when CNV is high, and vice versa.
I find a specification Tclsck (min 10ns) that defines CNV low to SCK rising edge. Fine. Probably CNV low to SCK falling edge is not critical? At least this is not specified!
So - is it OK to run a continuous SCK - if I make sure that the requirement is filled that there is no activity on the digital pins of the AD7949 around the rising edge of the CNV?
Any comments are highly appreciated. Need to get my prototype board going soon...
PS: First post here, great to have such a forum to discuss technical details!!!