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Test RX FMCOMMS2 (No-os)

Question asked by sangnt11 on Sep 2, 2015
Latest reply on Sep 2, 2015 by mhennerich

Dear!

I want to test RX port of IC AD9361 in FMCOMMS2 platform.

I using " AD9361 No-OS API " to config.

However, I config some case, it does not work.

Case 1:

     change data_port_loop_test_enable from "1" to "0" in file ad9361.h

#define DATA_PORT_LOOP_TEST_ENABLE     (1 << 0) /* Data Port Loop Test Enable */


Case 2:

     change from "ad9361_bist_loopback(phy, 1);" to "ad9361_bist_loopback(phy, 0);" in file ad9361_conv.c (line 403).

That disable ad9361_bist_loopback.


Case 3:

     change function ad9361_bist_loopback in file ad9361.c.

 

int32_t ad9361_bist_loopback(struct ad9361_rf_phy *phy, int32_t mode)

{

  uint32_t sp_hd, reg;

 

 

  dev_dbg(&phy->spi->dev, "%s: mode %"PRId32, __func__, mode);

 

 

  reg = ad9361_spi_read(phy->spi, REG_OBSERVE_CONFIG);

 

 

  phy->bist_loopback_mode = mode;

 

 

  switch (mode) {

  case 0:

  ad9361_hdl_loopback(phy, false);

  reg &= ~(DATA_PORT_SP_HD_LOOP_TEST_OE |

  DATA_PORT_LOOP_TEST_ENABLE);

  return ad9361_spi_write(phy->spi, REG_OBSERVE_CONFIG, reg);

  case 1:

  /* loopback (AD9361 internal) TX->RX */

 

 

 

 

  ad9361_hdl_loopback(phy, false);

  reg &= ~(DATA_PORT_SP_HD_LOOP_TEST_OE |

  DATA_PORT_LOOP_TEST_ENABLE);

  return ad9361_spi_write(phy->spi, REG_OBSERVE_CONFIG, reg);

 

 

 

 

  /*

  ad9361_hdl_loopback(phy, false);

  sp_hd = ad9361_spi_read(phy->spi, REG_PARALLEL_PORT_CONF_3);

  if ((sp_hd & SINGLE_PORT_MODE) && (sp_hd & HALF_DUPLEX_MODE))

  reg |= DATA_PORT_SP_HD_LOOP_TEST_OE;

  else

  reg &= ~DATA_PORT_SP_HD_LOOP_TEST_OE;

 

 

  reg |= DATA_PORT_LOOP_TEST_ENABLE;

 

 

  return ad9361_spi_write(phy->spi, REG_OBSERVE_CONFIG, reg);

  */

 

 

  case 2:

  /* loopback (FPGA internal) RX->TX */

 

 

 

 

  ad9361_hdl_loopback(phy, false);

  reg &= ~(DATA_PORT_SP_HD_LOOP_TEST_OE |

  DATA_PORT_LOOP_TEST_ENABLE);

  return ad9361_spi_write(phy->spi, REG_OBSERVE_CONFIG, reg);

 

 

 

 

  /*

  ad9361_hdl_loopback(phy, true);

  reg &= ~(DATA_PORT_SP_HD_LOOP_TEST_OE |

  DATA_PORT_LOOP_TEST_ENABLE);

  return ad9361_spi_write(phy->spi, REG_OBSERVE_CONFIG, reg);

  */

  default:

  return -EINVAL;

  }

}


That disable loopback in all case.

....

The script: bandwidth 5MHz, system_clock = 15.36MHz (2 channel).

When I change design, all of case, that are faulty:

- clock change from 15.36MHz to 61.44MHz.

- ad9361_init error.

- don't connect SMA rx port, output of AD9361 core have data (using ILA to catch chan_data, chan_valid, chan_enable in block design).

- Amplitude of adc_signal (RX) = -16dm of dac_signal (TX).


"

SAMPL CLK: 61440000 tuning: TX

  0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:

0:# # # # # # # # # # # # # # # #

1:# # # # # # # # # # # # # # # #

 

 

ad9361_dig_tune: Tuning TX FAILED!

ad9361_init : AD9361 initialization error

"

.....

I want to config to test RX port. For example, using 2 FMCOMMS2 platform, one platform to tranfer data, one platfrom receive data, 2 platform are connected by SMA connector.


Thanks and best regard.

Tien-Sang Nguyen.

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