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AD7193 accuracy issue

Question asked by adamg. on Sep 1, 2015
Latest reply on Oct 4, 2015 by KRZ

I am interfacing Pmod AD5 ADC which has a AD7193 chip with FPGA. I am able to get a 24 bit digital ouput code when an input is supplied. I am though facing problem related to the accuracy of conversion. When I give a constant dc value from a power supply as an analog input I only get 10-12 bits accurate data, the rest bits keep on varying each time. I have gone through the datasheet of AD7193 and looked into the tables of RMS noise and peak-to-peak noise. The error which I am getting is very large compared to those tables.

As per the need of my system I require an accuracy of atleast 10^(-6).


According to my understanding, to increase the accuracy, following should be done -:


ii)Output data rate (as the conversion and settling time depends on it)

iii)Choice of filter (sinc3/sinc4, chop enable disable)

The system requires the conversion to take place in very less time (within milliseconds). So I need to set a high output data rate (may be 960/1200/2400/4800 Hz) so that the conversion time is very less. It is also not possible to use chop enable, as its conversion time is very high.

For my system it is also not possible to perform system calibration each time.

I am using a single conversion mode.

But still for sinc4, chop disable, output data rate=960Hz according to the datasheet (as mentioned in the tables), ADC should give 21 bits accuracy.

I am doing the following steps in my code

i)Reset the ADC     (40 1's are passed)

ii)Write to mode register   (x280004)

iii)Write to configuration reg (x000110)

iv)Write to mode reg (x880004) for Internal zero scale calibration

v)Initiate a conversion (An input for when to start a conversion is taken from the user)

Again write x280004 into the mode reg for single conversion mode.

vi)Wait for RDY' to return low  to read the data.

(One thing which I have noticed is, though the data sheet says it takes a complete settling time for a conversion i.e. RDY' will return low after a complete settling time, but in my case its hardly requiring any time (after some microseconds RDY' returns low and I read the data; its not taking up a settling time which would be in milliseconds) )

So I think it might be possible that the output is not fully settled, but if that's the case then how come RDY' returns low.

v)Read the data register.

I have not seen any post related to the accuracy on this forum. Am I the only one who is facing this issue? And also one more question, how do you test your ADC to find out whether it is working properly or not? Is there any other method of testing that I should use?

Please help out... please..