How do I interface to multiple AD779x ADCs over the same serial interface ?
A single microcontroller/DSP can be used to communicate with several AD779x devices. The CS input of the ADC can be used to enable or disable the serial interface of the ADC. By controlling the CS inputs to the ADCs using a decoder, the microcontroller/DSP can communicate with each ADC individually or simultaneously. The following figure shows the interface between a microprocessor and several ADCs. The CS input of each ADC is connected to the decoder. Using the decoder, the microprocessor can select the ADC with which it wants to transfer data/instructions. When CS is high, the serial interface of the ADC is disabled and it ignores any activity on the data bus. To communicate with the ADC, its CS line can be taken low. The ADC will then have access to the data bus between itself and the microprocessor. The data sheet should be consulted for timing specifications.
I have a different configuration interface in my system.
Q1) Is this configuration valid?
Registers 0, 1, 2, 4, and 5 work very well with 2 CSn signaled
Register 3 works very well with single CSn signaled
Register 3 on one of the AD7792 misses bits as soon as a second RTD is connected
Sometimes one bit is missed, sometimes up to 4. Any of the missings makes the reading to be bad.
Missing of bits always occurs with the same AD7792 chip.
We are evaluating AD779x, so I don't have more for replacing and make more tests.
Please, if Q1's answer is yes, could you try to reproduce my configuration?
Both AD7792 cannot work having 'Clock Source' for Register 2 (MODE) as 'internal'. Instead:
Q2) Can you read both AD7792 values without missing any bits?
Thanks in advance,
All was my fault .
I was mixing
Eval has PullUp resistors for SPI communication, and mine doesn't.
All was controlled by an FPGA with no PullUp constraints specified for SPI pins.
I recognized a pattern that when REG(03) data had 101 it was always output as 11, having a very short time of 0 after first 1:
I guess a 1 to 0 for SCLK + PullUp sometimes could be seen as 1 to 0 to 1 to 0 making an unexpected rise of SCLK, an thus a new data bit... so lastly missing bits.
The corrected and working scenario has these modifications:
Thanks for reading
good to see that you have resolved your issue.
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