Hi, I hope get two parameter of AD9361 in burst model.
1 lock time of fast AGC of AD9361 in burst model
2 how long between AD9361 get RF signal of burst at input port and RX_frame valid?
Moved to Wide Band RF Transceivers.
Typical convergence time for LTE10 at 30.72MHz ClkRF data rate is about 10us. This can be further improved by running the part at 61.44MSPS sample rate and 122.88MHz ClkRF. Only minimum AGC convergence time could be specified, but it depends on clock speed and part configuration.
To maximize AGC algorithm convergence speed is to run the part at maximum output data rate which in turn will maximize ClkRF at 122.88MHz. AGC is clocked by ClkRF and the faster the ClkRF the faster the AGC operates.
RX_FRAME is driven by the AD9361 to identify valid data for the Rx data path (both P0 and P1). A high transition indicates the beginning of the frame. RX_FRAME can be set to be a single high transition at the beginning of a burst and stay high throughout the burst, or it can be set to be a pulse train that has a rising edge at the beginning of each frame (50% duty cycle). In CMOS mode, this signal is output from the RX_FRAME_P pin (RX_FRAME_N can be left unconnected). RX_FRAME indicates when you should be capturing digital port data. It is not an indicator of whether the data is "valid" data. AD9361 has no knowledge of that. You need to keep track of timing at a system level.
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