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SPI driver clears TIM, causes interesting results on bus

Question asked by jpetras on Aug 28, 2015
Latest reply on Oct 14, 2015 by jpetras

Hi All,


We ran into an interesting problem and found the answer, as posted here. I hope to save people a little trouble and perhaps get a little feedback from AD FAE brass.


We are running the SPIH interface to sent out a test loop of 10 byte sequences at 250kHz with 40ms between TX. However, we would get incorrect bus transactions. Further, the incorrect transaction would change based upon whether we would use DMA or not:


1. SPIH, non-DMA, 10-bytes, blocking or non-blocking, 250kHz = We see 11 bytes on the interface with the last byte value repeated


2. SPIH, DMA, 10-bytes, blocking or non-blocking, 250kHz = We see a transaction on the bus, but the TX Complete flag does not get set. Thus, only one transaction hits the bus.


The solution was the TIM bit. The SDK code clears the bit by default. We changed the driver to set the bit and now everything works like it should.


AD FAEs: any thoughts to add to this?