I use AD9911 in my design. we have LVPECL driver to drive differential clock to REF_CLK+/- of AD9911. I want to add Thevenin termination at AD9911. But I found in the datasheet of AD9911, it says Reference clock in first mode (logic low), ".. must be ac-coupled to the input due to internal dc biasing." my question is, Thevenin termination will provide 2V common-mode voltage at REF_CLKx inputs, Does this termination will affect internal DC biasing? If yes, what is the best termination for LVPECL clock input?