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Concerned about crystal/clock swing level/ ADC noise issue.

Question asked by alex12345 on Aug 28, 2015
Latest reply on Sep 2, 2015 by KJBob

Hello, I'm slightly concerned that the amplitude of my clock signal is too great.

 

Attachment 'PIN41_27PF' shows the signal at pin 41 of my ADAU1446 (after the 100R resistor), measured using an inch long ground lead. Scope set to .1V/div with 10x probe, so 1V/div visible. The lower half of the clock swings to around -0.4V, I don't know if this pin counts as a digital input, if it does, maximum input level is -0.3V. Should I be worried?

 

Attachment 'CLKOUT' shows the signal on the CLKOUT line, after a 100R series resistor, lower values give a 'less desirable' trace. Does this look OK?

 

These were taken with 27pF for the crystal compensation caps, using 22pF looks much the same. I daresay I could decrease further (or increase) the cap value and reduce the swing, but at the expense of stability?

 

Attachment 'PIN42' shows the signal at pin 42, the side of the crystal without the 100R resistor.

 

This has all come about because I'm seeing a lot of noise from my ADC, -54dBFS, which doesn't appear to be on the analog inputs. Measured using the level detector within sigmastudio. Have used all recommended decoupling and filtering etc...So looking to see where else the problem might be. Curiously sigmastudio almost always shows the value as -54 but occasionally shows it to be -60, with no change in hardware. I have the ADAU1445 set to be master, by changing it to be slave, noise reduces by 6dB, not sure what to make of that.

 

Attachment BCLK shows the BCLK signal to the ADC, (DSP is master). The trace is about an inch long and I can't noticeably that trace by tweaking the value of the series termination resistor (0r, 10r, 22r, 33r, 47r, 56r, 68r, 75r). Which has me wondering if there's a clock issue.

 

Any thoughts, thank you.

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