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SPI CLK

Question asked by tanjack on Aug 28, 2015
Latest reply on Aug 31, 2015 by tanjack

Hi,

According to ADSP-214xx SHARC Processor Hardware Reference (Page 16-7),the value of PCLK is 200 MHz.And in most of examples(such as 21479 AD1939 C Block-based talkthrough),we can set the SPIBAUD through the equation( Master Baud Rate = PCLK/(4 × BAUDR)) in the function SetupSPI1939.

So my question is where is  the value of PCLK from.In the file init_PLL_SDRAM,there is only the CCLK(266)and SCLK(133).

And according to ADSP-214xx SHARC Processor Hardware Reference (Page 23-6),the peripheral clock is derived from the core clock with a fixed post divisor of 2.

I can't understand these.Is there any problem in my comprehension?

 


Thanks,

Jack

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