I have some problems.
1. How to set the register, make the adv7282m into "free run mode".
2. I capture a wave for csi-2 interface. It must be a error signal. Which situation can cause this. attach is D0P signal.
Free run operation is explained on page 32 of http://www.analog.com/media/en/technical-documentation/evaluation-documentation/ADV7280_7281_7282_UG-637.pdf
Let me check with specialist on ADV7282m for second question.
Analog devices' scripts contain a free-run script to force the ADV7282-M to output a color bars test pattern. Analog devices' recommended scripts are available on engineering zone's ADV7282 design support files. :ADV7282 and ADV7282-M Design Support Files
I have seen this issue before. When you see incorrect voltage levels such as this then it implies that the backend processor is not terminating the MIPI CSI-2 signals correctly. The MIPI D-PHY in the backend processor must detect the mode of operation that the ADV7282-M is in (high speed or low power) and dynamically change its input impedance. If it does not do so then you can see incorrect voltage levels such as the ones you see.
To prove this is the issue: If you can disconnect the ADV7282-M from the backend processor and probe the MIPI traces then you will probably see that the issue goes away.
I have written an applications note (AN-1337) to help debug this and other issues you may have when interfacing the ADV7272-M. This is also available at engineering zone's ADV7282 design support files:
ADV7282 and ADV7282-M Design Support Files
Senior Applications Engineer,
DVP Group,Analog Devices Inc.
Can you give me some advice to solve this issue. The document(AN-1337) we have read. But we can't found some method. In this file, main to describe how to detect and give some layout tips. no solution be mentioned.
We disconnect the mipi csi2 signal line from imx6 cpu. But the wave incorrect still. follow is schematic and wave. Ours oscilloscope have 60Mhz bandwidth and 1GS/s sample rate.
1. We can't found "termination on" flag in the wave.
2.What is means with "The MIPI D-PHY in the backend processor must detect the mode of operation that the ADV7282-M is in (high speed or low power) and dynamically change its input impedance" which you mentions.
3. In single end input mode, do we need DIAG pin? We hand the pin with NC now.
I advise that you read the MIPI D-PHY and CSI-2 specification. The D-PHY specification shows how the MIPI signals goes from high speed to low power mode and vice versa. You can also see MIPI Video Output Specifications section of the ADV7282 datasheet for some information.
The signal you show in the oscilloscope plot is what I expected MIPI CSI-2 D0 output to be when not connected to a receiver. It shows a number of high speed to low power transitions.
The ADV7282-M is outputting MIPI CSI-2 information correctly. You are probably feeding this MIPI CSI-2 signal into a microprocessor. The experiment you performed proved that the microprocessor has not been programmed correctly. The microprocessor needs to terminate the signal correctly. Its input impedance needs to dynamically change to meet the output format from the ADV7282-M. This termination is usually performed by a piece of hardware called the D-PHY physical layer. This can be internal or external to the microprocessor.
As this is not an issue with the ADV7282-M I cannot help you resolve this. I suggest you contact your microprocessor vendor. Ensure that you have the latest MIPI CSI-2 software drivers for your microprocessor.
The diagnostic pin is entirely optional. You can leave the diagnostic pins not connected (i.e. floating) if not needed.
Layout tips for laying MIPI traces is given on last page of AN-1337.
We capture a complete wave like attachment. It is a correct still?
No this looks wrong. Please read Voltage Level Test section of AN-1337.
Quote from AN-1337:
When properly terminated, the data lines switch between HS and LP modes, as shown in Figure
2. In LP mode, the data lines have a logic high voltage of approximately 1.2 V and a logic low
voltage of approximately 0 V. In HS mode, the data lines have a logic high voltage of approximately 0.3 V and a logic low voltage of approximately 0.1 V.
If any logic level other than 1.2 V, 0.3 V, 0.1 V, or 0 V appears, the D-PHY layer of the MIPI CSI-2 receiver is not correctly terminating the output from the ADV7280-M, ADV7281-M, ADV7281-MA, or ADV7282-M transmitter device.
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