Our customer try to evaluate AD9625 Eva. Board (AD9625-2.0EBZ) using Xilinx KC705 by connecting FMC. However they can not establish the link of JESD204B by 4 lane. They use Xilinx JESD204B IP core. And they set up the registor of AD9625 to 4 lane ( 0x05E =0x04). Sampling rate is 1024Msps.
On the othere hand, the customer's board, which is used D9625, can establish the link to KC705 by 6 lane and 8 lane. But it also can not establish the link by 4.
Do you have any idea about the cause of this problem?