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AD9467 PN Issue

Question asked by wmaguire on Aug 25, 2015
Latest reply on Aug 27, 2015 by larsc

Hi all,


When we run the reference design as per Zedboard all works as expected.  We subsequently ported this design to our hardware where we have some differences.  First due to our PCB layout issues we needed to flip the polarities on several of the data bits as well as the DCO signal.  These changes are addressed by modifying the adc_dmux code  axi_ad9467_if.v as shown below and ensuring that the negative clock edge is use to clock all related processes.


The problem we have is we can detect the correct fixed test patterns correctly but we can not get the PN9 or PN23 sequences to sync.

So no problem with test patterns 0x80008000, 0xFFFFFFFF, 0x00000000, 0xAAAA5555 and 0xFFFF0000.  All work as expected.

As far as we can tell the code we use to setup the PN sequences is as per the Zedboard example.

We tried to alter the edge select and as expected this causes the standard test patterns to fail ie 0x80008000 goes to 0x40004000, 0xAAAA5555 -> 0x5555AAAA

If we take a 1024 ADC output sample upload from the ILA from the Zedboard and run it in the simulator the PN syncs as expected.  We can even remove samples in this file and the PN sequence locks.  If we try the same with our samples it never locks.  What is confusing is why would the the test patterns work but not the PN sequences given the data samples captured and feeding the PN should be correct as per pattern test results.








always @(negedge adc_clk) begin

      adc_data_p <= adc_data_p_s;

      adc_data_n <= adc_data_n_s;

      adc_data_p_d <= adc_data_p;

      adc_dmux_a <= (adc_ddr_edgesel == 1'b1) ? adc_data_n   : adc_data_p;

      adc_dmux_b <= (adc_ddr_edgesel == 1'b1) ? adc_data_p_d : adc_data_n;

      adc_data[15] <= ~adc_dmux_b[7];                 // PN Reversed ports, D15,D14, D13,D12, D11,D10, D7, D5,D6, DCO,DOR

      adc_data[14] <= ~adc_dmux_a[7];

      adc_data[13] <= ~adc_dmux_b[6];

      adc_data[12] <= ~adc_dmux_a[6];

      adc_data[11] <= ~adc_dmux_b[5];

      adc_data[10] <= ~adc_dmux_a[5];

      adc_data[ 9] <= adc_dmux_b[4];

      adc_data[ 8] <= adc_dmux_a[4];

      adc_data[ 7] <= ~adc_dmux_b[3];

      adc_data[ 6] <= ~adc_dmux_a[3];

      adc_data[ 5] <= ~adc_dmux_b[2];

      adc_data[ 4] <= ~adc_dmux_a[2];

      adc_data[ 3] <= adc_dmux_b[1];

      adc_data[ 2] <= adc_dmux_a[1];

      adc_data[ 1] <= adc_dmux_b[0];

      adc_data[ 0] <= adc_dmux_a[0];

      adc_or_p <= ~adc_or_p_s;

      adc_or_n <= ~adc_or_n_s;

      if ((adc_or_p == 1'b1) || (adc_or_n == 1'b1)) begin

        adc_or <= 1'b1;

      end else begin

        adc_or <= 1'b0;