I'm wondering if there's any linux driver available, or something for a similar product, for the HMC832 (formerly) Hittite fractional-N PLL + VCO device?
Sorry, at the moment there is no driver support for any of the HMC PLLs.
Did you make any headway with the Linux driver for the HMC832? I'm in the same boat trying to control it through their eval board using Ubuntu.
No, it turns out I just came back to revisit this very recently. Preparing to start our own driver... But trying to understand the SPI mode they've described in the datasheet...
From the datasheet SPI timing diagrams it looks like SDI and SDO are on opposite polarities, which doesn't look like any modes I can see anywhere else. Inserted here is a drawing from the datasheet that shows what I mean... SDI and SDO data appears to be valid on opposite phases. Other issues make this appear to be a non-standard SPI interface as well (device writes on SDO without any chip-select active signal).
The timing diagram describes the signals from the HMC832 perspective. The chip clocks SDI data in and sends LD/SDO data out on the rising SCK edge. Since the LD/SDO pin is multiplexed between SPI read data and lock detect we use the SEN rising edge to switch the multiplexer. Between SPI access a high LD/SDO signal indicates lock (by default).
If you want to write your own high level SPI interface FTDI does provide USB Linux drivers to control the low level SPI signals. You can use our USB interface board with the HMC832 eval board like we do with Windows 7.
Thank you for the information. During a Read operation by the master, does this mean that the data clocked out on SDO by the HMC832 chip is stable and can be read by the bus master on the rising edge of SCK? Or that it is written out on the rising edge, and must be read on the falling edge of SCK?
We are writing an embedded driver, so it cannot be through USB. I'm trying to understand whether we can set the SPI controller in a CPOL=1, CPHA=1 mode for this device and it will successfully write and read?
Related, we'd like to share these devices on the same SPI bus and to be able to read data from the PLL registers on the SDO line. But it looks like the device is always writing to SDO on every SPI operation, regardless of the state of the SEN line (per the 1st paragraph on page 31 of datasheet). So it seems that the device can't share the SDO line with other devices unless we keep its output permanently tri-stated (i.e., from datasheet: "To disable the driver completely, set Register 0x08 = 0 (it takes precedence over all else.)") ?
Your master should use CPOL=1 and CPHA=1 but you need two cycles to perform a single read. The 1st 32 rising edges on SCK send the read address to the HMC832 on SDI. The next 33 rising SCK edges sample lock detect followed by 32 bit SDO data as shown in figure 48. Master SCK to SDO hold time must be less than the 8.2ns SDO delay specified for the HMC832.
You can attach multiple devices on a single SDO line but individual SEN signals are required. To change devices tri-state the active device driving SDO by sending a SPI access with non-zero chip address. On the rising edge of SEN the device detects a non-zero chip address and tri-states SDO.
I'm trying to understand how this SDO sharing will work, but am still confused. If all I want to do in a message is write to a register on the device, then I send a 32-bit message on SDI, including a valid '000' binary chip address, so that the device will latch this message into its register.
However, on the next clocks to this bus (even if communicating with some other device on the bus), the HMC832 that was just written will start writing out on the SDO line, writing the contents of one of its registers onto SDO (based on whatever register address was last written to register 0). Is this correct?
So does this mean that in order to write to one register, when my next communication on this bus may be to a different device, I have to actually hold the bus (chip select) and write twice to this device? The first write would be the valid message and '000' binary chip address, followed by a write with any INVALID (non-zero) 3-bit chip address? This will then prevent it from writing on SDO until it gets the next valid write message?
I am also unclear on why the following step is included in the "two part read cycle" (or "Serial Port Read Operation") messaging, but not included in the write message...
9. The master clears SEN to complete the the address transfer of the two part read cycle.
Why is clearing SEN necessary to complete the address transfer of a READ operation, but not necessary in a WRITE operation?
Thanks for the response. I have the Hittite HMC832 eval board with the USB interface, but the sample Linux code hangs on the read. The Windows app supplied with the board works fine, but I need to develop this on Linux. Have you tried to interface with the HMC832 from Linux? I'd like to know if I can read/write directly to /dev/ttyUSB0 or if I have to use the FTDI D2xx driver. Also, since the FTDI examples don't work, I'm looking for a short example like reading register 0x00 for the chip id, etc. Thanks in advance.
We haven't used any of the Linux code. I think you need to go through the D2xx driver since this interface is defined by FTDI. Maybe FTDI could help.
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