I am using a 25MHz crystal on the AD9910 along with the phase-locked loop (PLL) multiplier. The desired result is a 1.0 GHz system clock rate. I am using a frequency multiplication factor of 40 (decimal), thinking that 25MHz x 40 = 1GHz. However, it appears that the system clock is running at 500MHz - exactly half the rate that I need.

I'm setting the PLL multiplication factor using CFR3, with bits [7:0] set to 0x28 (i.e. decimal 40). Looking at SYNC_OUT is see a square wave with frequency 31.25MHz. According to the datasheet, this should be 1/16 of the system clock frequency, so 31.25MHz x 16 = 500MHz.

What am I doing wrong?

Hi,

You did nothing wrong. However you just need an additional configuration.

That is, set CFR3 [15] = 1. This will disable the /2 divider (input divider is bypassed). The default of this is the input divider is selected.

Hope that helps.