for my master thesis I am implementing a user ip core in the receiving part of the refernce design (between the AD9361 and the ADC_DMA). I am using the Zedboard and the FMCOMMS2.
Now, I have the following problem. When I am trying to test the system with a known signal (sinusoidal signal) I am getting at the quadrature-component a disturbed sinusoidal signal, whereas the inphase-component is the known signal. The quadrature-component looks like getting overlapped by noise. Furthermore, I connected the I and Q signal to the ILA in front of my costum IP Core.
Is it possible that this problem arise by timing failure?
When I am testing the Reference design without my IP Core I can see the inphase as well as the quadrature component without any disturbances.