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ADF4158 CP output noise

Question asked by bitbad on Aug 19, 2015
Latest reply on Aug 24, 2015 by rbrennan



    There is a problem about ADF4158 CP output noise (or called jitter) puzzles me a lot recently. The setting file ADF4158_settings_FSK_with_ramp.txt attached is generated with ADF4158/9 PLL software revision 4.10.5, which is used to configure a continuous sawtooth with FSK ramp waveform, and the settings are simulated with ADIsimPLL correctly. As is shown in figure FSK_with_ramp_4158.png attached, Δf is 960kHz and f_step is -480kHz, and time per step is 25.6us. Accordingto to the VCO in use, 2.5mV voltage change can result in 480kHz frequency change. Unfortunately, the jitter of ADF4158 CP output is about 30mV measured with oscilloscope in each step of the waveform, which is far higher than the 2.5mV voltage change needed. As a result, there is no difference between period A and period B in figure FSK_with_ramp_4158.png according to the final waveform shown on the oscilloscope screem. The 480kHz frequency difference is usefull to me in my system in fact, however, I could not get the waveform simulated with SDIsimPLL software.


    Can you tell me how to lower the jitter of ADF4158 CP output? What is the main factor of the jitter or noise, the loop filter design or the jitter of  thep ower of ADF4158 in the system, or some other factors?


   Trying to solve the problem, I mesure 3.3V power on circuit board and find out that the 3.3V power itself exsists a 25mV jitter, and I don't know whether this phenomenon leads to the problem mentioned above.


Can you give me some suggestions about the problem? Is there any precision limittion of ADF4158?



Many thanks!