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SPORT0 I2S interrupt

Question asked by spetca on Aug 19, 2015
Latest reply on Sep 21, 2015 by SachinV

Hi I have a BF592 setup as follows

 

void init_interrupts(void)

{

  register_handler(ik_ivg9, SPORT0_Tx_ISR);

  ssync();

}

 

 

//initialize sport0

void init_sport0(void)

{

 

  *pSPORT0_TCR1 = 0x0000;

  *pSPORT0_RCR1 = 0x0000;

  *pSPORT0_TCR2 = 0x0000;

  *pSPORT0_RCR2 = 0x0000;

  ssync();

 

 

  *pSPORT0_TCR2   |=  TSFSE  | SLEN(15);

  ssync();

 

  *pSPORT0_TCR1   |=  TCKFE  | TFSR  ;

  ssync();

 

 

  *pSPORT0_RCR2   |=  RSFSE  | SLEN(15);

  ssync();

 

  *pSPORT0_RCR1   |=  RCKFE  | RFSR   ;

  ssync();

 

*pSIC_IMASK0   |= IRQ_DMA1;

 

  *pSPORT0_RCR1 = (*pSPORT0_RCR1 | RSPEN); /* enable sport0 RX */

 

  *pSPORT0_TCR1 = (*pSPORT0_TCR1 | TSPEN); /* enable sport0 TX */

  ssync();

 

}

 

 

EX_INTERRUPT_HANDLER(SPORT0_Tx_ISR)

{

  static int TXcnt = 0;

  static int RXcnt = 0

static int frameCount = 0;

  static int junk;

 

  *pDMA1_IRQ_STATUS = DMA_DONE;

  *pDMA2_IRQ_STATUS = DMA_DONE;

 

  *pPORTGIO ^= PG4;

 

  BufferRx[RXcnt] = *pSPORT0_TX16;

  *pSPORT0_TX16   = BufferTx[TXcnt];

 

if(frameCount =- BuffRxLen*2)

{

    // disable interrupts

}

 

frameCount ++;

}

 

 

I expect that the pin PG4 should toggle once per frame sync and that maybe PG4 should  toggle BuffRxLen*1/(Bit clock frequency) into the frame? I know the interrupt is asserted anytime the Rx FIFO has received a word which seems it should happen every 16*(1/bit clock frequency)...But PG4 seems to toggle about 4 times and does not align with the frame sync.

 

I am attempting to keep track of the left and right frame syncs in order to discard the right frame sync data as its receiving from a codec output which is mono, but i2s (data is in left frame). Also need to keep track of frame syncs to time the delay of received data from the codec because the codec filters have a delay as a function of the sampling rate (frequency of LR frame sync)

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