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ADAU1701 I2S IN-I2S OUT @ 96kHz

Question asked by dan_xerx on Aug 19, 2015
Latest reply on Oct 28, 2016 by DaveThib

Hi all,

 

I've been testing a platform that consists of ADC-DSP set-up with DSP as a slave to the ADC. The ADC feeds the DSP with I2S at 96kHz and a MCLK of 12.288MHz.  PLL setting on the ADAU1701 is 256*fs, DSP core at 2x(512 instructions), serial out at 96kHz, 6MHz bclk out (see attached file). To make the story short, I need a 12.288MHz input clock work for a 96kHz system with I2S in and I2S out.

 

Three things I've done so far:

1. The DSP can successfully read the I2S but it cannot output the I2S and I have tried the 48kHz(DSP core and serial output) set up and      it works fine. 

2. Tried to tie up LRCK_OUT and BCLK_OUT to LRCK_IN and BCLK_IN, respectively but to no avail. reference: https://ez.analog.com/message/167656#167656

 

3. Tried to input a 24MHz clock (bypass ADC) and 96kHz I2S from an AP machine and it works fine.

 

Can someone give suggestion on what is wrong with the set-up? Do I need to supply the DSP with clock of 24Mhz crystal in order to produce a 96kHz I2S output?

 

Regards,

Dan

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