I got one customer using AD9361 for SDR application. They would like to find out below info:
1) PLL lock time for the AD9361 based on largest hop bandwidth?
For example, if between f0 to f50 is 500 MHz, then what is the PLL lock time when the LO it changes from f0 to f50?
2) What is the minimum step-size of the analog filter of AF9361 be it in TX or RX path ? What will be the configurations for the filters?
Thanks and BR