We have been trying to use another vendor's JESD204B DAC for our application, but were surprised by errors in their datasheet. The latency was spec'd at 11 DAC clock cyles (which in hindsight seems ridiculously low). After continual asking, the other vendor steered us to another datasheet that had MUCH higher values of latency specified. The actual latency we measured from sending values from the FPGA across the JESD204B link to final output of the DAC on the order of 550ns.
So, now we are looking for another DAC since we are trying to run this DAC as part of a closed loop feedback system with as low as latency as possible.
From the AD9144 Data sheet, I see the following:
Interface 17 = PClock cycles
Interpolation 1 = 58 DAC clock cycles
If we are clocking at 370 MHz.
DataRate = (DACRate)/(InterpolationFactor)
LaneRate = (20 × DataRate × M)/L
Since interpolationFactor i1 1 (for our case) the Lane rate is 20*370/L. Setting L=1 means our Lane rate would be 7.4 Gbps.
And, PClock would be 185 MHz.
So, if I add up the latency per the data sheet, I should see:
17/185e6 + 58/370e6 = 248 ns. Due to the DAC alone. Disregarding our latency due to our serialization and link length. Is this what we should expect from this part? Delays on the order of 250 ns? Thanks in advance!